My fpga study notes
Sep 14, 2016: The 'Hello World' example with Verilog
1. Install Yosys under Ubuntu.
> sudo add-apt-repository ppa:saltmakrell/ppa
> sudo apt-get update
> sudo apt-get install yosys
2. Get the Verilog code hello.v here.
3. Run the following command.
> yosys -p 'read_verilog hello.v'
4. Instead, we can bring up the Yosys prompy. Then type the same command.
> yosys
yosys>read_verilog hello.v
5. We shall see the output as follows.
>1. Executing Verilog-2005 frontend.
Parsing Verilog input from `hello.v' to AST representation.
Generating RTLIL representation for module `\hello'.
Hello world!
Successfully finished Verilog frontend.
A few good self-study sites and Q&A pages
1. Quick tutorial to write Verilog with PaPilio
write to me: yulung at gmail dot com
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